finn.util.fpgadataflow (module)

class finn.util.fpgadataflow.IPGenBuilder

Bases: object

Builds the bash script to generate IP blocks using Vivado HLS.

append_tcl(tcl_script)

Sets member variable “tcl_script” to given tcl script.

build(code_gen_dir)

Builds the bash script with given parameters and saves it in given folder. To guarantee the generation in the correct folder the bash script contains a cd command.

set_ipgen_path(path)

Sets member variable ipgen_path to given path.

finn.util.fpgadataflow.is_fpgadataflow_node(node)

Returns True if given node is fpgadataflow node. Otherwise False.

finn.util.fpgadataflow.pyverilate_get_liveness_threshold_cycles()

Return the number of no-output cycles rtlsim will wait before assuming the simulation is not finishing and throwing an exception.

finn.util.fpgadataflow.pyverilate_stitched_ip(model)

Given a model with stitched IP, return a PyVerilator sim object.

finn.util.fpgadataflow.rtlsim_multi_io(sim, io_dict, num_out_values, trace_file='')

Runs the pyverilator simulation by passing the input values to the simulation, toggle the clock and observing the execution time. Function contains also an observation loop that can abort the simulation if no output value is produced after a set number of cycles. Can handle multiple i/o streams. See function implementation for details on how the top-level signals should be named.

sim: the PyVerilator object for simulation io_dict: a dict of dicts in the following format:

{“inputs”{“in0”<input_data>, “in1”<input_data>},

“outputs” : {“out0” : [], “out1” : []} }

<input_data> is a list of Python arbitrary-precision ints indicating what data to push into the simulation, and the output lists are similarly filled when the simulation is complete

num_out_values: number of total values to be read from the simulation to

finish the simulation and return.

returns: number of clock cycles elapsed for completion