finn.util.pyverilator (module)

finn.util.pyverilator.axilite_read(sim, addr, basename='s_axi_control_')

Read val from addr on AXI lite interface given by basename.

Arguments: - sim : PyVerilator sim object - addr : address for read - basename : prefix for AXI lite interface name

Returns: read value from AXI lite interface at given addr

finn.util.pyverilator.axilite_write(sim, addr, val, basename='s_axi_control_', wstrb=15, sim_addr_and_data=True)

Write val to addr on AXI lite interface given by basename.

Arguments: - sim : PyVerilator sim object - addr : address for write - val : value to be written at addr - basename : prefix for AXI lite interface name - wstrb : write strobe value to do partial writes, see AXI protocol reference - sim_addr_and_data : handshake AW and W channels simultaneously

finn.util.pyverilator.multi_handshake(sim, ifnames, basename='s_axi_control_')

Perform a handshake on list of interfaces given by ifnames. Will assert VALID and de-assert after READY observed, in as few cycles as possible.

finn.util.pyverilator.reset_rtlsim(sim, rst_name='ap_rst_n', active_low=True)

Sets reset input in pyverilator to zero, toggles the clock and set it back to one

finn.util.pyverilator.toggle_clk(sim, clk_name='ap_clk')

Toggles the clock input in pyverilator once.

finn.util.pyverilator.wait_for_handshake(sim, ifname, basename='s_axi_control_', dataname='DATA')

Wait for handshake (READY and VALID high at the same time) on given interface on PyVerilator sim object.

Arguments: - sim : PyVerilator sim object - ifname : name for decoupled interface to wait for handshake on - basename : prefix for decoupled interface name - dataname : interface data sig name, will be return value if it exists

Returns: value of interface data signal during handshake (if given by dataname), None otherwise (e.g. if there is no data signal associated with interface)